Improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. In an attempt to increase circuit density, three-dimensional (3D) integrated circuits (ICs) have been investigated. In a typical formation process of a 3D IC, two dies are bonded together and electrical connections are formed between each die and contact pads on a substrate. Interposer stacking is part of 3D IC technology where a through-silicon via (TSV) embedded interposer is connected to a device silicon with a micro bump. 3D IC manufacturing process flows can be separated into two types. In a chip-on-chip-on-substrate (CoCos) process flow, a silicon interposer chip is first attached onto a packaging substrate, and then a different device silicon chip is attached onto the interposer. In a chip-on-wafer-on-substrate (CoWoS) process flow, a device silicon chip is first attached onto a silicon interposer wafer, which is then diced. The resulting stacked silicon is then attached onto a substrate.
However, when more devices are put into one chip, more complex designs are required. A system on chip (SOC) has multiple metal layers, not all components on the SOC require advanced process. The processing to all the metal layers vary depending on many factors, for example, pitch. A processing without discrimination to different metal layers is likely to result in high production cost.